Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPC Challenge Benchmark Suite

Workshop:H2RC 2020: Sixth International Workshop on Heterogeneous High-Performance Reconfigurable Computing

Authors: Marius Meyer, Tobias Kenter, and Christian Plessl (Paderborn University)

Abstract: FPGAs have found increasing adoption in data center applications since a new generation of high-level tools has become available which noticeably reduces development time for FPGA accelerators and still provides high-quality results. There is, however, no high-level benchmark suite available, which specifically enables a comparison of FPGA architectures, programming tools and libraries for HPC applications.

To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community.

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