SC20 Proceedings

The International Conference for High Performance Computing, Networking, Storage, and Analysis

Scalable yet Rigorous Floating-Point Error Analysis

Authors: Arnab Das, Ian Briggs, and Ganesh Gopalakrishnan (University of Utah); Sriram Krishnamoorthy (Pacific Northwest National Laboratory (PNNL), Washington State University); and Pavel Panchekha (University of Utah)

Abstract: Automated techniques for rigorous floating-point round-off error analysis are a prerequisite to placing important activities in HPC such as precision allocation, verification and code optimization on a formal footing. Yet existing techniques cannot provide tight bounds for expressions beyond a few dozen operators; barely enough for HPC. In this work, we offer an approach embedded in a new tool called SATIRE that scales error analysis by four orders of magnitude compared to today’s best-of-class tools. We explain how three key ideas underlying SATIRE help it attain such scale; path strength reduction, bound optimization and abstraction. SATIRE provides tight bounds and rigorous guarantees on significantly larger expressions with well over a hundred thousand operators, covering important examples including FFT, matrix multiplication and PDE stencils.

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