Daniele De Sensi is currently a Postdoctoral Researcher in the Scalable Parallel Computing Laboratory (SPCL) at ETH Zurich. He got his Ph.D. in Computer Science from the University of Pisa, Italy. His doctoral work focused on autonomic and power-aware runtime solutions for parallel applications. He has designed and implemented algorithms and tools to enforce power consumption and performance requirements on parallel applications through dynamic reconfigurations of computing resources. His current research interests lie in the fields of HPC interconnection networks and in-network computing. He co-authored more than 30 publications on power-aware computing, parallel computing, and high-performance interconnection networks.