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Fast Stencil-Code Computation on a Wafer-Scale Processor
Event Type
Paper
Tags
Accelerators, FPGA, and GPUs
Applications
Architectures
Registration Categories
TP
TimeWednesday, 18 November 20201pm - 1:30pm EST
LocationTrack 4
DescriptionThe performance of CPU-based and GPU-based systems is often low for PDE codes, where large, sparse and often structured systems of linear equations must be solved. Iterative solvers are limited by data movement, both between caches and memory and among nodes. Here we describe the solution of such systems of equations on the Cerebras Systems CS-1, a wafer-scale processor that has the memory bandwidth and communication latency to perform well. We achieve 0.86 PFLOPS on a single wafer-scale system for the solution by BiCGStab of a linear system arising from a 7-point finite difference stencil on a 600 × 595 × 1536 mesh, achieving about one third of the machine’s peak performance. We explain the system, its architecture and programming and its performance on this problem and related problems. We discuss issues of memory capacity and floating point precision. We outline plans to extend this work toward full applications.
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