Ch’i: Scaling Microkernel Capabilities in Cache-Incoherent Systems
Event Type
Workshop
System Software and Runtime Systems
W
TimeFriday, 13 November 20201:30pm - 2pm EDT
LocationTrack 7
DescriptionHardware cache coherence limits the scalability of shared-memory multicore and multi-processors. Recently, there has been an increasing shift toward cache-incoherent architectures in many computing environments. Supercomputers can benefit from shared memory, yet must avoid the price of coherency across the system. To support co-locating multiple applications on cores, processors and the overall system, an operating system (OS) must manage the distributed memory resources. In this context, incoherence poses a significant challenge for an OS that must manage memory access permissions across the system without compromising the performance of software.
In this paper, we introduce the Ch’i microkernel that leverages incoherent shared memory using quiescence-based techniques to bound the extent of non-coherency. Ch’i maintains type and context consistency of its core data structures: capabilities. This enables a uniform, capability-based security model to manage system-wide memory. Using this approach, we demonstrate data-structure consistency in software in support of high-throughput, low-latency applications.
In this paper, we introduce the Ch’i microkernel that leverages incoherent shared memory using quiescence-based techniques to bound the extent of non-coherency. Ch’i maintains type and context consistency of its core data structures: capabilities. This enables a uniform, capability-based security model to manage system-wide memory. Using this approach, we demonstrate data-structure consistency in software in support of high-throughput, low-latency applications.