Integrating FPGAs in a Heterogeneous and Portable Parallel Programming Model
TimeThursday, 19 November 20208:30am - 5pm EDT
DescriptionThe programmability of FPGAs has been simplified by high level synthesis languages (HLS) and techniques, like OpenCL. These reduce the programming effort, but the user has to take care of details related to command queue management, data transfers and synchronization. The Controller heterogeneous programming model proposes a higher-level approach with fully portable host codes, and a runtime-managed library of kernel versions that can be specialized for different device types and families. It is implemented as a compiler-agnostic C99 library. It supports CPU-core sets, GPUs using CUDA or OpenCL and Xeon Phi devices. This work introduces support for FPGAs in the Controller model. We consider offline compilation, transparent synchronous and asynchronous execution modes and new kernel parameters for FPGAs. Experimental results show almost negligible performance overhead and a high reduction of development effort compared with OpenCL.