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Compute Express Link™ (CXL™) and Gen-Z Protocols: Bridging the Resource Gap Between CPU, Memory and Accelerators
Event Type
Panel
Tags
Architectures
Collaborative Environments
Data Analytics, Compression, and Management
Networks
Registration Categories
TP
TimeWednesday, 18 November 20201pm - 2:30pm EST
LocationTrack 6
DescriptionCompute Express Link™ (CXL™) and Gen-Z are low-latency, memory-semantic (read/write) protocols that enable the transition to memory-centric architectures. CXL provides coherent, point-to-point solutions with emphasis on node-level computing, while the core design of Gen-Z is fabric-based and focuses on connectivity at the rack and row level.

The CXL Consortium™ and Gen-Z Consortium™ recently announced a Memorandum of Understanding (MoU) agreement to leverage the complementary aspects of both technologies. The agreement outlines the formation of common workgroups to define bridging between the two protocols.

In this panel, attendees will learn how HPC applications and solutions are optimized by these emerging technologies, as well as examine why, where and how to deploy them architecturally.
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