Intelligent, Reconfigurable Data Orchestration in FPGA and Embedded FPGA for Machine Learning Applications
Accelerators, FPGA, and GPUs
TimeTuesday, 17 November 202011am - 11:30am EDT
DescriptionThere is a proliferation of silicon devices targeting Machine Learning (ML), ranging from fixed function silicon such as ASIC, through CPU, GPU, to reprogrammable FPGAs. In almost every instance, the more prosaic task of organizing and orchestrating the data receives relatively less attention, but arguably is most important. It does not matter how powerful your processing engine is, if you cannot get data to that engine; often this can result in an effective processing rate that is a small fraction of the peak. Furthermore, certain pre-processing tasks (such as data/weight compression, feature extraction or filtering) are not necessarily well suited to a processing engine optimized for matrix-vector mathematics (MVM) that forms the basis of much ML processing.
In this contribution, we explore how FPGA fabric can efficiently implement the manifold tasks associated with data orchestration, including interface adaption (for new or changing standards), data payload extraction, sensor fusion (for disparate datastreams), data compression and pre-processing. In general, the fine-grained reprogrammable FPGA architecture is well suited to the bitwise processing that comprise this data orchestration stage.
This can be a standalone FPGA aggregating external interfaces/memory and connecting multiple ML SOCs. Alternatively, embedded FPGA (eFPGA) has emerged in recent years as a method for enabling flexibility when integrated within an SOC. In this application, eFPGA would implement the functions which flexibility is required, for example due to application specific IO or sensor fusion requirements. This could be coupled with a dedicated MVM engine for an optimized, low cost solution for edge deployment.