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UID:submissions.supercomputing.org_SC20_sess328_exforum124@linklings.com
SUMMARY:Intelligent, Reconfigurable Data Orchestration in FPGA and Embedde
 d FPGA for Machine Learning Applications
DESCRIPTION:Exhibitor Forum\n\nIntelligent, Reconfigurable Data Orchestrat
 ion in FPGA and Embedded FPGA for Machine Learning Applications\n\nFitton,
  Nijssen, Roge\n\nThere is a proliferation of silicon devices targeting Ma
 chine Learning (ML), ranging from fixed function silicon such as ASIC, thr
 ough CPU, GPU, to reprogrammable FPGAs.  In almost every instance, the mor
 e prosaic task of organizing and orchestrating the data receives relativel
 y less attention, but arguably is most important.  It does not matter how 
 powerful your processing engine is, if you cannot get data to that engine;
  often this can result in an effective processing rate that is a small fra
 ction of the peak.  Furthermore, certain pre-processing tasks (such as dat
 a/weight compression, feature extraction or filtering) are not necessarily
  well suited to a processing engine optimized for matrix-vector mathematic
 s (MVM) that forms the basis of much ML processing.   \n\nIn this contribu
 tion, we explore how FPGA fabric can efficiently implement the manifold ta
 sks associated with data orchestration, including interface adaption (for 
 new or changing standards), data payload extraction, sensor fusion (for di
 sparate datastreams), data compression and pre-processing.  In general, th
 e fine-grained reprogrammable FPGA architecture is well suited to the bitw
 ise processing that comprise this data orchestration stage.  \n\nThis can 
 be a standalone FPGA aggregating external interfaces/memory and connecting
  multiple ML SOCs.  Alternatively, embedded FPGA (eFPGA) has emerged in re
 cent years as a method for enabling flexibility when integrated within an 
 SOC.  In this application, eFPGA would implement the functions which flexi
 bility is required, for example due to application specific IO or sensor f
 usion requirements.  This could be coupled with a dedicated MVM engine for
  an optimized, low cost solution for edge deployment.\n\nTag: Accelerators
 , FPGA, and GPUs, Architectures\n\nRegistration Category: Exhibits Reg Pas
 s
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