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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20210402T160547Z
LOCATION:Track 12
DTSTART;TZID=America/New_York:20201109T100000
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UID:submissions.supercomputing.org_SC20_sess248_tut113@linklings.com
SUMMARY:Productive Parallel Programming for FPGA with High-Level Synthesis
DESCRIPTION:Tutorial\n\nProductive Parallel Programming for FPGA with High
 -Level Synthesis\n\nde Fine Licht, Hoefler\n\nEnergy efficiency has become
  a first class citizen in the design of large computing systems. While GPU
 s and custom processors show merit in this regard, reconfigurable architec
 tures, such as FPGAs, promise another major improvement in energy efficien
 cy, constituting a middle ground between fixed hardware architectures and 
 custom-built ASICs. This tutorial shows how high-level synthesis (HLS) can
  be harnessed to productively achieve scalable pipeline parallelism on FPG
 As. Attendees will learn how to target FPGA resources from high-level C++ 
 or OpenCL code, guiding the mapping from imperative code to hardware, enab
 ling them to develop massively parallel designs. We treat well-known examp
 les from the software world, relating traditional code optimizations to ha
 rdware, building on existing knowledge when introducing new topics. By bri
 dging the gap between software and hardware optimization, our tutorial aim
 s to enable developers from a large set of backgrounds to start tapping in
 to the potential of FPGAs for high performance codes.\n\nTag: Accelerators
 , FPGA, and GPUs, Heterogeneous Systems, Parallel Programming Languages, L
 ibraries, and Models, Software Engineering\n\nRegistration Category: Tutor
 ial Reg Pass
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