BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/New_York
X-LIC-LOCATION:America/New_York
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20210402T160558Z
LOCATION:Track 2
DTSTART;TZID=America/New_York:20201113T111000
DTEND;TZID=America/New_York:20201113T114000
UID:submissions.supercomputing.org_SC20_sess221_ws_p3hpc102@linklings.com
SUMMARY:Tracking Performance Portability on the Yellow Brick Road to Exasc
 ale
DESCRIPTION:Workshop\n\nTracking Performance Portability on the Yellow Bri
 ck Road to Exascale\n\nDeakin, Poenaru, Lin, McIntosh-Smith\n\nWith exasca
 le machines on our immediate horizon, there is a pressing need for applica
 tions to be made ready to best exploit these systems. However, there will 
 be multiple paths to exascale, with each system relying on processor and a
 ccelerator technologies from different vendors. As such, applications will
  be required to be portable between these different architectures, but it 
 is also critical that they are efficient too. These double requirements fo
 r portability and efficiency begets the need for performance portability. 
 In this study we survey the performance portability of different programmi
 ng models, including the open standards OpenMP and SYCL, across the divers
 e landscape of exascale and pre-exascale processors from Intel, AMD, NVIDI
 A, Fujitsu, Marvell, and Amazon, together encompassing GPUs and CPUs based
  on both x86 and Arm architectures. We also take a historical view and ana
 lyze how performance portability has changed over the last year.\n\nRegist
 ration Category: Workshop Reg Pass
END:VEVENT
END:VCALENDAR

