BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/New_York
X-LIC-LOCATION:America/New_York
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20210402T160554Z
LOCATION:Track 4
DTSTART;TZID=America/New_York:20201111T162000
DTEND;TZID=America/New_York:20201111T163000
UID:submissions.supercomputing.org_SC20_sess201_ws_ia113@linklings.com
SUMMARY:Performance Evaluation of the Vectorizable Binary Search Algorithm
 s on an FPGA Platform
DESCRIPTION:Workshop\n\nPerformance Evaluation of the Vectorizable Binary 
 Search Algorithms on an FPGA Platform\n\nJin, Finkel\n\nField-programmable
  gate arrays (FPGAs) are becoming promising heterogeneous computing compon
 ents. In the meantime, high-level synthesis (HLS) tools are pushing the FP
 GA-based development from the register-transfer level to high-level-langua
 ge design flow using Open Computing Language (OpenCL), C, and C++. The per
 formance of binary search applications is often associated with irregular 
 memory access patterns to off-chip memory. In this paper, we implement the
  binary search algorithms using OpenCL, and evaluate their performance on 
 an Intel Arria-10 based FPGA platform. Based on the evaluation results, we
  implement the grid search in XSBench by vectorizing and replicating the b
 inary search kernel. In addition, we overcome the overhead of kernel vecto
 rization by grouping work-items into work-groups. Our optimizations improv
 e the performance of the grid search using the classic binary search by a 
 factor of 1.75 on the FPGA.\n\nRegistration Category: Workshop Reg Pass
END:VEVENT
END:VCALENDAR