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DTSTART:19700308T020000
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DTSTAMP:20210402T160558Z
LOCATION:Track 5
DTSTART;TZID=America/New_York:20201111T153000
DTEND;TZID=America/New_York:20201111T160000
UID:submissions.supercomputing.org_SC20_sess195_ws_mchpc104@linklings.com
SUMMARY:Understanding the Impact of Memory Access Patterns in Intel Proces
 sors
DESCRIPTION:Workshop\n\nUnderstanding the Impact of Memory Access Patterns
  in Intel Processors\n\nMonil, Lee, Vetter, Malony\n\nDue to increasing co
 mplexity in the memory hierarchy, predicting the performance of a given ap
 plication in a given processor is becoming more difficult. The problem is 
 worsened by the fact that the hardware needed to deal with more complex me
 mory traffic also affects energy consumption.  Moreover, in a heterogeneou
 s system with shared main memory, the memory traffic between the last leve
 l cache (LLC) and the memory creates contention between other processors a
 nd accelerator devices. For these reasons, it is important to investigate 
 and understand the impact of different memory access patterns on the memor
 y system. \n\nThis study investigates the interplay between Intel processo
 rs' memory hierarchy and different memory access patterns in applications.
   The authors explore streaming and strided memory access patterns with th
 e objective of predicting LLC-DRAM traffic for a given application in give
 n Intel architectures.  Moreover, the impact of prefetching is also invest
 igated in this study.  Experiments with different Intel micro-architecture
 s uncover mechanisms to predict LLC-DRAM traffic that can yield up to 99% 
 accuracy for streaming access patterns and up to 95% accuracy for strided 
 access patterns.\n\nRegistration Category: Workshop Reg Pass
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