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LOCATION:Track 4
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UID:submissions.supercomputing.org_SC20_sess175_pap545@linklings.com
SUMMARY:Accelerating Sparse DNN Models without Hardware-Support via Tile-W
 ise Sparsity
DESCRIPTION:Paper\n\nAccelerating Sparse DNN Models without Hardware-Suppo
 rt via Tile-Wise Sparsity\n\nGuo, Hsueh, Leng, Qiu, Guan...\n\nNetwork pru
 ning can reduce the high computational cost of deep neural network (DNN) m
 odels.  To maintain their accuracies, however, sparse models often carry r
 andomly-distributed weights, leading to irregular computations. Consequent
 ly, sparse models cannot achieve meaningful speedup on commodity hardware 
 (e.g., GPU) built for dense matrix computations. As such, prior works usua
 lly modify or design completely new sparsity-optimized architectures for e
 xploiting sparsity. We propose an algorithm-software co-designed pruning m
 ethod that achieves latency speedups on existing dense architectures.\n\nO
 ur work builds upon the insight that the matrix multiplication generally b
 reaks the large matrix into multiple smaller tiles for parallel execution.
  We propose a tiling-friendly "tile-wise'' sparsity pattern, which maintai
 ns a regular pattern at the tile level for efficient execution but allows 
 for irregular, arbitrary pruning at the global scale to maintain high accu
 racy. We implement and evaluate the sparsity pattern on GPU tensorcore, ac
 hieving a 1.95x speedup over the dense model.\n\nTag: Accelerators, FPGA, 
 and GPUs, Machine Learning, Deep Learning and Artificial Intelligence, Spa
 rse Computation\n\nRegistration Category: Tech Program Reg Pass
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